This invention relates to a semiconductor integrated circuit, and more particularly to an electrically logic programmable circuit.
Electrically programmable devices of a relatively large scale are generally called Field Programmable Gate Arrays (hereinafter abbreviated as a FPGA). FPGA can be independently programmed at logic circuits for carrying out logical operations and at wiring formation sections for switching connecting states between signal lines. In a conventional FPGA, as shown in FIG. 16, a region 50 where logic circuits are formed and regions 51-54 where wiring formation sections are formed are physically separated. Also, in a FPGA shown in FIG. 17, a region 60 where logic circuits are formed and regions 61-64 where wiring formation sections are formed are separated. In FIG. 17, reference symbols IOB 65-70 represent regions where blocks for input/output circuits are provided, respectively.
The outline of the configuration of such a conventional FPGA is shown in FIG. 18, and the principle of the operation thereof will be described below. As described above, the FPGA is divided into three fundamental or basic components (elements) of a block (CLB) 81 where logic circuits are formed, a wiring formation section 82, and an input/output circuit block (IOB) 83. The logic circuit block 81 is a block in which basic logical elements are combined to perform logical operations, and includes a combination logic section 81a and flip-flop sections 81b, 81c as shown in FIG. 19. The wiring formation section 82 serves to connect respective logic circuit blocks 81 to each other and is adapted so that switching of connections can be freely made by programming. In addition, the input/output circuit block 83 is a section where circuits for interfacing between the device and external are formed. Similarly, programming can be made therein.
These three fundamental elements are such that alterations of functions can be respectively made by programming so that a desired specification can be set. Setting of the specification can be desirably changed by rewriting the contents of program memories corresponding to respective fundamental elements, with a relationship of one-to-one correspondence.
However, the conventional FPGAs mentioned above have the following problems. Although it is necessary that the ratio between respective areas of the logic circuit blocks 81 and the wiring formation sections 82 be set to an optimum value in order to realize miniaturization of the device, such a ratio varies to a large degree, in dependency upon the specification of the entire logic functions.
Even with an FPGA using the same logic circuit elements 91-94 as shown in FIGS. 20(a) and (b), a required quantity of wirings varies to a large degree, in dependency upon the entire logic circuit functions.
However, in conventional FPGAs, there is no compatibility between the logic circuit block and the wiring formation section, and setting of the area ratio is uniformly determined. For this reason, in dependency upon the specification of the device, there are instances where the area utilization efficiency is remarkably low. Such problems have become increasingly conspicuous with improvements in the degree of integration. In addition, in attempting to carry out extension or expansion of the scale of the device corresponding to the progress of the semiconductor miniaturization technology, because the logic sections and the wiring sections are separately formed, there are difficulties in expanding or extending.